CCLKS=0, TSEG2=000, SJW=00, TSEG1=0000
Bit Configuration Register
| CCLKS | CAN Clock Source Selection 0 (0): PCLK (generated by the PLL clock) 1 (1): CANMCLK (generated by the main clock) |
| TSEG2 | Time Segment 2 Control 0 (000): Setting prohibited 1 (001): 2 Tq 2 (010): 3 Tq 3 (011): 4 Tq 4 (100): 5 Tq 5 (101): 6 Tq 6 (110): 7 Tq 7 (111): 8 Tq |
| SJW | Resynchronization Jump Width Control 0 (00): 1 Tq 1 (01): 2 Tq 2 (10): 3 Tq 3 (11): 4 Tq |
| BRP | Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK). |
| TSEG1 | Time Segment 1 Control 0 (0000): Setting prohibited 1 (0001): Setting prohibited 2 (0010): Setting prohibited 3 (0011): 4 Tq 4 (0100): 5 Tq 5 (0101): 6 Tq 6 (0110): 7 Tq 7 (0111): 8 Tq 8 (1000): 9 Tq 9 (1001): 10 Tq 10 (1010): 11 Tq 11 (1011): 12 Tq 12 (1100): 13 Tq 13 (1101): 14 Tq 14 (1110): 15 Tq 15 (1111): 16 Tq |